HARDWARE-AWARE PERFORMANCE OPTIMIZATION OF YOLOV8 FOR REAL-TIME APPLICATIONS: GPU ACCELERATION WITH TENSORRT AND AN ANALYTICAL FPGA COMPARISON
DOI:
https://doi.org/10.5281/zenodo.20781147Abstract
Real-time computer-vision systems deployed on edge platforms are constrained as much by the surrounding software
pipeline and the host–accelerator interface as by raw compute. This paper presents a reproducible, hardware-aware optimization study
of the lightweight YOLOv8n object detector on an NVIDIA Tesla T4 GPU and contrasts the measured GPU behavior against an
analytical projection of a Xilinx Zynq UltraScale+ (ZU9EG) FPGA accelerator. Applying TensorRT graph optimization—vertical
Conv–BatchNorm–activation layer fusion together with FP16 precision—raised single-stream inference throughput on the T4 from a
PyTorch FP32 baseline of 62.92 FPS to 72.72 FPS, a 1.16× (15.6%) speed-up, while mean average precision on COCO val2017 fell
only marginally ([email protected] from 52.8% to 52.6%). A controlled batch-size sweep then exposes a host-side preprocessing bottleneck:
as the batch grows to 16, host CPU utilization saturates to 98%, while GPU utilization decreases to 8%, and end-to-end throughput
degrades to 2.05 effective FPS. We show analytically and empirically that this is a data-ingest (decode/resize) limitation of the host
pipeline rather than a compute limit of the accelerator. Finally, using device datasheets and published FPGA-accelerator figures, we
project that a spatial INT8 dataflow accelerator would deliver lower peak throughput (≈45 FPS) but markedly better energy efficiency
and deterministic per-frame latency, characteristics desirable for latency-critical edge deployment. All numerical claims are clearly
separated into measured (GPU) and projected (FPGA) categories.
Keywords
object detection; YOLOv8; TensorRT; layer fusion; FP16/INT8 quantization; GPU; FPGA; edge inference; energy efficiency; deterministic latency.References
Jocher, G.; Chaurasia, A.; Qiu, J. Ultralytics YOLOv8. GitHub Repository, 2023. Available online: https://github.com/
ultralytics/ultralytics (accessed on 16 May 2026).
NVIDIA. TensorRT Developer Guide: Optimizing Inference. NVIDIA Corporation, 2024. Available online: https://docs.
nvidia.com/deeplearning/tensorrt/ (accessed on 16 May 2026).
AMD Xilinx. Vitis AI User Guide (UG1414), Version 3.5. AMD, 2023. Available online: https://docs.amd.com/r/en-US/
ug1414-vitis-ai (accessed on 16 May 2026).
Wang, C.Y.; Bochkovskiy, A.; Liao, H.Y.M. YOLOv7: Trainable Bag-of-Freebies Sets New State-of-the-Art for Real-
Time Object Detectors. arXiv:2207.02696, 2022. Available online: https://arxiv.org/abs/2207.02696 (accessed on 16 May
.
Han, S.; Mao, H.; Dally, W.J. Deep Compression: Compressing Deep Neural Networks with Pruning, Trained
Quantization and Huffman Coding. In Proceedings of the International Conference on Learning Representations
(ICLR), San Juan, Puerto Rico, 2–4 May 2016.
Redmon, J.; Divvala, S.; Girshick, R.; Farhadi, A. You Only Look Once: Unified, Real-Time Object Detection. In
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition (CVPR), Las Vegas, NV, USA,
–30 June 2016; pp. 779–788.
Bochkovskiy, A.; Wang, C.Y.; Liao, H.Y.M. YOLOv4: Optimal Speed and Accuracy of Object Detection. arXiv:2004.10934,
Available online: https://arxiv.org/abs/2004.10934 (accessed on 16 May 2026).
NVIDIA. Jetson Nano Developer Kit User Guide. NVIDIA Corporation, 2019. Available online: https://developer.download.
nvidia.com/embedded/L4T/r32-3-1_Release_v1.0/Jetson_Nano_Developer_Kit_User_Guide.pdf (accessed on 16 May 2026).
Asano, S.; Maruyama, T.; Yamaguchi, Y. Performance Evaluation of FPGA-Based DNN Accelerators. IEEE Micro,
, 41, 34–42.
Qiu, J.; Wang, J.; Yao, S.; Guo, K.; Li, B.; Zhou, E.; Yu, J.; Tang, T.; Xu, N.; Song, S.; Wang, Y.; Yang, H. Going
Deeper with Embedded FPGA Platform for Convolutional Neural Network. In Proceedings of the 2016 ACM/SIGDA
International Symposium on Field-Programmable Gate Arrays (FPGA ’16), Monterey, CA, USA, 21–23 February 2016;
pp. 26–35.
Howard, A.; Sandler, M.; Chu, G.; Chen, L.C.; Chen, B.; Tan, M.; Wang, W.; Zhu, Y.; Pang, R.; Vasudevan, V.; Le, Q.V.;
Adam, H. Searching for MobileNetV3. In Proceedings of the IEEE/CVF International Conference on Computer Vision
(ICCV), Seoul, Republic of Korea, 27 October–2 November 2019; pp. 1314–1324.
Tan, M.; Le, Q.V. EfficientNet: Rethinking Model Scaling for Convolutional Neural Networks. In Proceedings of the
th International Conference on Machine Learning (ICML), Long Beach, CA, USA, 9–15 June 2019; pp. 6105–6114.
AMD Xilinx. Zynq UltraScale+ MPSoC Data Sheet: Overview (DS891). AMD, 2025. Available online: https://docs.amd.
com/v/u/en-US/ds891-zynq-ultrascale-plus-overview (accessed on 16 May 2026).
Jouppi, N.P.; Young, C.; Patil, N.; Patterson, D.; Agrawal, G.; Bajwa, R.; Bates, S.; Bhatia, S.; Boden, N.; Borchers,
A.; Boyle, R.; Cantin, P.; Chao, C.; Clark, C.; Coriell, J.; Daley, M.; Dau, M.; Dean, J.; Gelb, B.; Ghaemmaghami,
T.V.; Gottipati, R.; Gulland, W.; Hagmann, R.; Ho, C.R.; Hogberg, D.; Hu, J.; Hundt, R.; Hurt, D.; Ibarz, J.; Jaffey, A.;
Jaworski, A.; Kaplan, A.; Khaitan, H.; Killebrew, D.; Koch, A.; Kumar, N.; Lacy, S.; Laudon, J.; Law, J.; Le, D.; Leary,
C.; Liu, Z.; Lucke, K.; Lundin, A.; MacKean, G.; Maggiore, A.; Mahony, M.; Miller, K.; Nagarajan, R.; Narayanaswami,
R.; Ni, R.; Nix, K.; Norrie, T.; Omernick, M.; Penukonda, N.; Phelps, A.; Ross, J.; Ross, M.; Salek, A.; Samadiani,
E.; Severn, C.; Sizikov, G.; Snelham, M.; Souter, J.; Steinberg, D.; Swing, A.; Tan, M.; Thorson, G.; Tian, B.; Toma,
H.; Tuttle, E.; Vasudevan, V.; Walter, R.; Wang, W.; Wilcox, E.; Yoon, D.H. In-Datacenter Performance Analysis of a
Tensor Processing Unit. In Proceedings of the 44th Annual International Symposium on Computer Architecture (ISCA),
Toronto, ON, Canada, 24–28 June 2017; pp. 1–12.
Sze, V.; Chen, Y.H.; Yang, T.J.; Emer, J.S. Efficient Processing of Deep Neural Networks: A Tutorial and Survey.
Proceedings of the IEEE, 2017, 105(12), 2295–2329.
Jacob, B.; Kligys, S.; Chen, B.; Zhu, M.; Tang, M.; Howard, A.; Adam, H.; Kalenichenko, D. Quantization and Training
of Neural Networks for Efficient Integer-Arithmetic-Only Inference. In Proceedings of the IEEE/CVF Conference on
Computer Vision and Pattern Recognition (CVPR), Salt Lake City, UT, USA, 18–22 June 2018; pp. 2704–2713.
Krishnamoorthi, R. Quantizing Deep Convolutional Networks for Efficient Inference: A Whitepaper. arXiv:1806.08342,
Available online: https://arxiv.org/abs/1806.08342 (accessed on 16 May 2026).
Gholami, A.; Kim, S.; Dong, Z.; Yao, Z.; Mahoney, M.W.; Keutzer, K. A Survey of Quantization Methods for Efficient
Neural Network Inference. arXiv:2103.13630, 2021. Available online: https://arxiv.org/abs/2103.13630 (accessed on 16
May 2026).
Lin, T.Y.; Maire, M.; Belongie, S.; Hays, J.; Perona, P.; Ramanan, D.; Dollár, P.; Zitnick, C.L. Microsoft COCO: Common
Objects in Context. In Proceedings of the European Conference on Computer Vision (ECCV), Zurich, Switzerland,
–12 September 2014; pp. 740–755.
Deng, J.; Dong, W.; Socher, R.; Li, L.J.; Li, K.; Fei-Fei, L. ImageNet: A Large-Scale Hierarchical Image Database. In
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition (CVPR), Miami, FL, USA, 20–25
June 2009; pp. 248–255.
Ultralytics. YOLOv8 Documentation. Ultralytics, 2024. Available online: https://docs.ultralytics.com/models/yolov8/
(accessed on 16 May 2026).
NVIDIA. TensorRT 10.0.1 Release Notes. NVIDIA Corporation, 2024. Available online: https://docs.nvidia.com/
deeplearning/tensorrt/latest/getting-started/release-notes-10/10.0.1.html (accessed on 16 May 2026).
Mittal, S. A Survey of FPGA-Based Accelerators for Convolutional Neural Networks. Neural Computing and Applications,
, 32, 1109–1139.
Shawahna, A.; Sait, S.M.; El-Maleh, A. FPGA-Based Accelerators of Deep Learning Networks for Learning and
Classification: A Review. IEEE Access, 2019, 7, 7823–7859.
Venieris, S.I.; Kouris, A.; Bouganis, C.S. Toolflows for Mapping Convolutional Neural Networks on FPGAs: A Survey
and Future Directions. ACM Computing Surveys, 2018, 51(3), Article 56.
Cong, J.; Xiao, B. Minimizing Memory Accesses in FPGA-Based Acceleration of Deep Convolutional Neural Networks.
In Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2018.
Alwani, M.; Chen, H.; Ferdman, M.; Milder, P. Fused-Layer CNN Accelerators. In Proceedings of the 49th Annual IEEE/
ACM International Symposium on Microarchitecture (MICRO), Taipei, Taiwan, 15–19 October 2016.
Zhang, C.; Li, P.; Sun, G.; Guan, Y.; Xiao, B.; Cong, J. Optimizing FPGA-Based Accelerator Design for Deep Convolutional
Neural Networks. In Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA ’15), Monterey, CA, USA, 22–24 February 2015; pp. 161–170.
Ma, Y.; Cao, Y.; Vrudhula, S.; Seo, J.S. An Automatic RTL Compiler for High-Throughput FPGA Implementation
of Diverse Deep Convolutional Neural Networks. In Proceedings of the 27th International Conference on Field
Programmable Logic and Applications (FPL), Ghent, Belgium, 4–8 September 2017.
Guo, K.; Sui, L.; Qiu, J.; Yu, J.; Wang, J.; Yao, S.; Han, S.; Wang, Y.; Yang, H. Angel-Eye: A Complete Design Flow
for Mapping CNN onto Embedded FPGA. IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 2018, 37(1), 35–47.
Downloads
Published
How to Cite
Issue
Section
